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UC3842/UC3843/UC3844/UC3845
SMPS Controller
Features
* * * * Low Start up Current Maximum Duty Clamp UVLO With Hysteresis Operating Frequency up to 500KHz
Description
The UC3842/UC3843/UC3844/UC3845 are fixed frequencycurrent-mode PWM controller. They are specially designed for Off-Line and DC to DC converter applications with minimum external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator and a high current totempole output for driving a Power MOSFET. The UC3842 and UC3844 have UVLO thresholds of 16V (on) and 10V (off). The UC3843 and UC3845 are 8.5V(on) and 7.9V (off). The UC3842 and UC3843 can operate within 100% duty cycle. The UC3844 and UC3845 can operate with 50% duty cycle.
8-DIP 8-SOP
1
1
14-SOP
1
Internal Block Diagram
* NORMALLY 8DIP/8SOP PIN NO. * ( ) IS 14SOP PINNO. * TOGGLE FLIP FLOP USED ONLY IN UC3844, UC3845
Rev. 1.0.1
(c)2002 Fairchild Semiconductor Corporation
UC3842/UC3843/UC3844/UC3845
Absolute Maximum Ratings
Parameter Supply Voltage Output Current Analog Inputs (Pin 2.3) Error Amp Output Sink Current Power Dissipation at TA25C (8DIP) Power Dissipation at TA25C (8SOP) Power Dissipation at TA25C (14SOP) Storage Temperature Range Lead Temperature (Soldering, 10sec) Symbol VCC IO V(ANA) ISINK (E.A) PD(Note1,2) PD(Note1,2) PD(Note1,2) TSTG TLEAD Value 30 1 -0.3 to 6.3 10 1200 460 680 -65 ~ +150 +300 Unit V A V mA mW mW mW C C
Note: 1. Board Thickness 1.6mm, Board Dimension 76.2mm x114.3mm, (Reference EIA / JSED51-3, 51-7) 2. Do not exceeed PD and SOA (Safe Operation Area)
Power Dissipation Curve
1200 8DIP 1100 POWER DISSIPATION (mW) 1000 900 800 700 600 500 400 300
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
14SOP
8SOP
AMBIENT TEMPERATURE ()
Thermal Data
Characteristic Thermal Resistance Junction-ambient Symbol Rthj-amb(MAX) 8-DIP 100 8-SOP 265 14-SOP 180 Unit C/W
Pin Array
8DIP,8SOP 14SOP
COMP 1
8
VREF
COMP 1
14 VREF
VFB 2
7
VCC
N/C
2
13
N/C
CURRENT SENSE
3
6
OUTPUT
VFB 3
12
VCC
RT/CT 4
5 GND
N/C 4
11 PWR VC
CURRENT SENSE
5
10 OUTPUT
N/C
6
9
GND
RT/CT 7
8
PWR GND
2
UC3842/UC3843/UC3844/UC3845
Electrical Characteristics
(VCC=15V, RT=10k, CT=3.3nF, TA= 0C to +70C, unless otherwise specified) Parameter REFERENCE SECTION Reference Output Voltage Line Regulation Load Regulation Short Circuit Output Current OSCILLATOR SECTION Oscillation Frequency Frequency Change with Voltage Oscillator Amplitude ERROR AMPLIFIER SECTION Input Bias Current Input Voltage Open Loop Voltage Gain Power Supply Rejection Ratio Output Sink Current Output Source Current High Output Voltage Low Output Voltage CURRENT SENSE SECTION Gain Maximum Input Signal Power Supply Rejection Ratio Input Bias Current OUTPUT SECTION Low Output Voltage High Output Voltage Rise Time Fall Time Start Threshold Min. Operating Voltage (After Turn On) VOL ISINK = 20mA ISINK = 200mA VOH tR tF ISOURCE = 20mA ISOURCE = 200mA TJ = 25C, CL= 1nF (Note 3) TJ = 25C, CL= 1nF (Note 3) UC3842/UC3844 UC3843/UC3845 UC3842/UC3844 UC3843/UC3844 13 12 14.5 7.8 8.5 7.0 0.08 1.4 13.5 13.0 45 35 16.0 8.4 10.0 7.6 0.4 2.2 150 150 17.5 9.0 11.5 8.2 V V V V ns ns V V V V GV VI(MAX) PSRR IBIAS (Note 1 & 2) Vpin1 = 5V(Note 1) 12V VCC 25V (Note 1,3) 2.85 0.9 3 1 70 -3 3.15 1.1 -10 V/V V dB A IBIAS VI(E>A) GVO PSRR ISINK ISOURCE VOH VOL Vpin1 = 2.5V 2V VO 4V (Note3) 12V VCC 25V (Note3) Vpin2 = 2.7V, Vpin1 = 1.1V Vpin2 = 2.3V, Vpin1 = 5V Vpin2 = 2.3V, RL = 15k to GND Vpin2 = 2.7V, RL = 15k to Pin 8 2.42 65 60 2 -0.6 5 -0.1 2.50 90 70 7 -1.0 6 0.8 -2 2.58 1.1 A V dB dB mA mA V V f f/VCC VOSC TJ = 25C 12V VCC 25V 47 52 0.05 1.6 57 1 kHz % VP-P VREF VREF VREF ISC TJ = 25C, IREF = 1mA 12V VCC 25V 1mA IREF 20mA TA = 25C 4.90 5.00 6 6 -100 5.10 20 25 -180 V mV mV mA Symbol Conditions Min. Typ. Max. Unit
UNDER-VOLTAGE LOCKOUT SECTION VTH(ST) VOPR(MIN)
3
UC3842/UC3843/UC3844/UC3845
Electrical Characteristics (Continued)
(VCC=15V, RT=10k, CT=3.3nF, TA= 0C to +70C, unless otherwise specified) Parameter PWM SECTION Max. Duty Cycle Min. Duty Cycle TOTAL STANDBY CURRENT Start-Up Current Operating Supply Current Zener Voltage IST ICC(OPR) VZ ICC = 25mA Vpin3=Vpin2=ON 30 0.45 14 38 1 17 mA mA V D(Max) D(Max) D(MIN) UC3842/UC3843 UC3844/UC3845 95 47 97 48 100 50 0 % % % Symbol Conditions Min. Typ. Max. Unit
Adjust VCC above the start threshould before setting at 15V
Note: 1. Parameter measured at trip point of latch 2. Gain defined as: V pin1 A = ----------------- ,0 Vpin3 0.8V V pin3 3. These parameters, although guaranteed, are not 100 tested in production.
UC3842
Figure 1. Open Loop Test Circuit
High peak currents associated with capacitive loads necessitate careful grounding techniques Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
4
UC3842/UC3843/UC3844/UC3845
UC3842/44 UC3843/45
Figure 2. Under Voltage Lockout
During Under-Voltage Lock-Out, the output driver is biased to a high impedance state. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with output leakage current.
Figure 3. Error Amp Configuration
Figure 4. Current Sense Circuit
Peak current (IS) is determined by the formula:
1.0V I S ( MAX ) = ----------RS
A small RC filter may be required to suppress switch transients.
5
UC3842/UC3843/UC3844/UC3845
Figure 5. Oscillator Waveforms and Maximum Duty Cycle
Oscillator timing capacitor, CT, is charged by VREF through RT and discharged by an internal current source. During the discharge time, the internal clock signal blanks the output to the low state. Selection of RT and CT therefore determines both oscillator frequency and maximum duty cycle. Charge and discharge times are determined by the formulas: tc = 0.55 RT CT
0.0063RT - 2.7 t D = R T C T I n --------------------------------------- 0.0063R T - 4
Frequency, then, is: f=(tc + td)-1
1.8 ForRT > 5K ,f = -------------RT CT
Figure 6. Oscillator Dead Time & Frequency
Figure 7. Timing Resistance vs Frequency
(Deadtime vs CT RT > 5k)
Figure 8. Shutdown Techniques
6
UC3842/UC3843/UC3844/UC3845
Shutdown of the UC3842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.
UC3842/UC3843
Figure 9. Slope Compensation
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%. Note that capacitor, CT, forms a filter with R2 to suppress the leading edge switch spikes.
Temperature (C) Figure 10. Temperature Drift (Vref)
Temperature (C) Figure 11. Temperature Drift (Ist)
Temperature (C) Figure 12. Temperature Drift (Icc)
7
UC3842/UC3843/UC3844/UC3845
Mechanical Dimensions
Package
8-DIP
1.524 0.10 0.018 0.004 0.060 0.004 0.46 0.10
6.40 0.20 0.252 0.008
#1
#8
#4
#5
9.20 0.20 0.362 0.008
9.60 MAX 0.378
(
0.79 ) 0.031
5.08 MAX 0.200 7.62 0.300 3.40 0.20 0.134 0.008
3.30 0.30 0.130 0.012 0.33 MIN 0.013
0.25 -0.05
+0.10
0~15
0.010 -0.002
+0.004
8
2.54 0.100
UC3842/UC3843/UC3844/UC3845
Mechanical Dimensions (Continued)
Package
8-SOP
MIN 1.55 0.20 0.061 0.008 0.1~0.25 0.004~0.001
#1
#8 4.92 0.20 0.194 0.008 5.13 MAX 0.202
( #4 #5 6.00 0.30 0.236 0.012
+0.10 0.15 -0.05 +0.004 0.006 -0.002
0.56 ) 0.022 1.80 MAX 0.071 MAX0.10 MAX0.004 3.95 0.20 0.156 0.008 5.72 0.225 0.50 0.20 0.020 0.008
0~
8
1.27 0.050
0.41 0.10 0.016 0.004
9
UC3842/UC3843/UC3844/UC3845
Mechanical Dimensions (Continued)
Package
14-SOP
MIN 1.55 0.10 0.061 0.004 0.05 0.002
#1
#14
8.70 MAX 0.343
8.56 0.20 0.337 0.008
#7 6.00 0.30 0.236 0.012
#8
1.80 MAX 0.071
+0.10 0.20 -0.05 +0.004 0.008 -0.002
3.95 0.20 0.156 0.008
0.60 0.20 0.024 0.008
5.72 0.225
10
0~
8
MAX0.10 MAX0.004
1.27 0.050
+0.10 0.406 -0.05 +0.004 0.016 -0.002
(
0.47 ) 0.019
UC3842/UC3843/UC3844/UC3845
Ordering Information
Product Number UC3842N UC3843N UC3844N UC3845N UC3842D1 UC3843D1 UC3844D1 UC3845D1 UC3842D UC3843D UC3844D UC3845D 14-SOP 8-SOP 0 ~ + 70C 8-DIP Package Operating Temperature
11
UC3842/UC3843/UC3844/UC3845
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 2/19/02 0.0m 001 Stock#DSxxxxxxxx 2002 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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